During their production, integrated semiconductor memories, for example DRAM (dynamic random access memory) semiconductor memories, undergo numerous tests at different levels before being sent to a customer. In general, integrated semiconductor memories are tested as early as during their production at the wafer level by contact tips of a tester being positioned at specially provided locations in the circuit layout, to measure important design parameters. If a memory module has successfully passed the functional test at the wafer level in the front end of a production line, the individual memory chips are removed from the wafer and the chips are welded in a housing. The finished housed memory module is subsequently subjected to a renewed functional test at the component or module level. The memory chips are tested individually during the test at the component level, whereas the functioning of the memory chips in a possible application is tested during the module test.
The tests at the component and module levels generally comprise a plurality of test steps that are typically carried out at different temperatures on a limited number of test receptacles. Due to thermomechanical effects and receptacle wear, contact faults can occur between the receptacle and test component. The failure rate is greatly dependent on the type of receptacle and the maintenance thereof, but is typically in the percentage range. To avoid rejecting defect-free devices which have not successfully passed a test due to contact faults, a second test with the same test conditions is generally carried out in the case of integrated semiconductor memories. All semiconductor chips which pass the test in the second test cycle are classified as defect-free modules. It is assumed, in this case, that a contact fault was the cause of the failure in the first test cycle.
However, this procedure is problematic with regard to marginal or sporadically failing memory modules. Sporadically failing modules are unstable failures, and upon multiple repetitions of a test, the specification, is met in an unforeseen manner during one test cycle and is not met during a later renewed test cycle with the same test conditions. Such unstable failures are based, for example, on charging effects of contact holes which have been affected by contamination residues as a result of a previous process, such as an etching process. In the case of marginally failing modules, so-called borderline cases, the measured parameters are at the specification limit. However, since the design parameters are generally measured with a sufficient test bias, the borderline cases constitute less of a problem in comparison to sporadic failure parts. By contrast, sporadically failing devices have to be regarded as a potential quality risk.
During a functional test, contact failures of integrated semiconductor memory chips can be differentiated from marginal or sporadic failures on the basis of the number of failed memory cells of a memory module. It has been shown that contact failures, which are caused for example by a poor contact between a data input terminal, command line or an address line and a contact terminal of the test receptacle, leads to a very high number of failure cells within a memory cell array of the semiconductor memory. In the case of marginally or sporadically failing semiconductor memories, the number of defective memory cells of a memory cell array is limited to significantly fewer individual cells than is the case with contact failures. In the case of a semiconductor memory having a memory capacity of 512 MB, the number of defects on account of marginally or sporadically failing memory cells is approximately 1000 individual cells per memory module, for example. This generally involves weak individual cells or defective bit or word lines.
To ensure improved production testing with regard to yield and quality, therefore, only memory modules in which the number of failed memory cells per test exceeds a specific threshold value should be approved for a repeat test, since the possible cause of error here, on account of the high number of defective memory cells during the first test cycle, is very probably attributable to a contact problem between measurement receptacle and test component. Such a differentiation of genuine and non-genuine contact faults of memory modules using the number of failing memory cells as a differentiation criterion during a test of the integrated semiconductor memory, cannot typically be carried out during production testing, however. This is due to the fact that existing test systems are generally not furnished with additional equipment which would permit the defects to be counted during a functional test. As the memory modules are becoming faster, the testing systems operate too slowly to detect defective individual memory cells or the number of defects that have occurred.